hsa_amd_ipc_memory_detach is called with an invalid mapped pointer.
Changed to pass the svm pointer of the owner memory instead.
Change-Id: I8203c6e2d718efb8ca3b028309bc78caff8d4c7d
[ROCm/clr commit: 5bb30d7718]
hsa_amd_memory_lock_to_pool() and hsa_amd_memory_unlock()
should be called balanced.
Change-Id: I8b1549861bff752aabbb6399d717d1e346079a38
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
[ROCm/clr commit: cc29df873a]
Recent changes disabled system memory allocation
in the abstraciton layer. That requires memory
allocation/destruction in ROCR. Add destruction logic.
Change-Id: I68fe6b0a620ca743fe5850052ea0efa8bb7931c2
[ROCm/clr commit: a6d480e098]
Add a view bit to avoid original resource destruction when parent
dependency doesn't exist with the image view cache
Change-Id: I8277afd575af8f29951c5d1a9f7d94d784251657
[ROCm/clr commit: b49e8e78e1]
Make sure parent_ field is cleared for the internal image views.
The internal image views don't require dependencies tracking.
The issue appeard only when Navi10 pitch workaround was enabled.
Change-Id: I376d212750085a9391f8c32fc2979dcb5d93c89c
[ROCm/clr commit: 6b89980fb2]
Blit manager requires an image view to reduce the amount
of copy kernels. Creation/destruction of a view in ROCr is
an expensive operation. Thus, runtime can cache views for fast access.
Change-Id: Ia67d775b481cc8326d91215ca22d4a73c1dddb59
[ROCm/clr commit: d29755452b]
let ROCr and addrlib decided whether a pitch is supported.
Then, check if we uses workaround.
Also improve image performance for Navi 1x in some cases.
Change-Id: If8bda46648b23c1dcfa26608ca3bb9cd89fef430
[ROCm/clr commit: b961d4a970]
- Make IPC interfaces generic between devices and rely on the IPC buffer
for attach/detach logic
Change-Id: Id3c18d122030329b7ee532bbb6317de9dd6a0bbe
[ROCm/clr commit: 9aa6f25f1c]
Rename VK interop to ExternalMemory object, since it should handle
DX interops also
Change-Id: I536ec46d3e53ece35234a2e29030393ad411b96d
[ROCm/clr commit: 3e5803c4c0]
Remove amdgpu-pro interface for persistent memory,
used in Liquidflash
Change-Id: I7d1720ad0875a62ebb2d7f96cba39601d560a5df
[ROCm/clr commit: 6dad2fc306]
For OCL, keep original control logic
FOr HIP, keep the fix for SWDEV-338781
Change-Id: I89de8d1e73cd103b3b4f62206eed72d45695dd6e
[ROCm/clr commit: 0a43f6bff3]
The heap must be cleared once per device, but ROCclr doesn't
create a queue per device in HIP. Hence, the clear operation will
be performed during the first queue creation.
Change-Id: I52ceb06d67d11cde6d019c5ab510059f426a9bfb
[ROCm/clr commit: 04bfd93569]
Pass active queue for transfers in the cache coherency layer.
That will allow to use device transfer queue only for
cases when active queue isn't available, because using device
transfer queue from another active queue may cause a deadlock
Change-Id: Ifbe7e0303b77dbf6eeda3939ffbc25a3df7472de
[ROCm/clr commit: 95d55fdfa8]
Current logic when creating a buffer view will end up going into the
allocation block. Even though no memory will be allocated, since
owner()->getSvmPtr() is already allocated, we'll still end up
calling updateFreeMemory().
Checking if we're creating a view, will skip the SVM allocation logic
and let us fall into the actual view creation logic. This won't end up
updating the free memory counter.
Change-Id: I1c260a9ef57895130b272ea1246e06e812b25b37
[ROCm/clr commit: f167136918]
kjayapra-amd
Ioannis Assiouras
Jaydeep Patel
German Andryeyev
Lang Yu
Alex Xie
Ajay
Sourabh Betigeri
Anusha GodavarthySurya
Julia Jiang
haoyuan2
Satyanvesh Dittakavi
Sarbojit Sarkar
pghafari
Saleel Kudchadker
Vladislav Sytchenko
Jason Tang