std::mem_fun() and std::bind2nd() are removed in c++17. Switch to
simpler logic that does not require those functions.
Change-Id: I19a31f076e1813e367615bd377b424046ce144c7
[ROCm/clr commit: d934612948]
CMake does not provide a way to query the NUMA library, hence we need
to find it manually.
Change-Id: I370b286acdee75cbebc21340da3c432c79f8ffa7
[ROCm/clr commit: dd23379ac8]
std: :mem_fun() is removed in c++17. Simplify logic to not require it.
Change-Id: Ic9a4753b48dd13fcb20cd5b90ff73c3df3211b9f
[ROCm/clr commit: c68f024b35]
Current logic when creating a buffer view will end up going into the
allocation block. Even though no memory will be allocated, since
owner()->getSvmPtr() is already allocated, we'll still end up
calling updateFreeMemory().
Checking if we're creating a view, will skip the SVM allocation logic
and let us fall into the actual view creation logic. This won't end up
updating the free memory counter.
Change-Id: I1c260a9ef57895130b272ea1246e06e812b25b37
[ROCm/clr commit: f167136918]
Redshift sees around a 3x performance uplift this change.
Turning this on for OpenCL might cause unwanted behaviour, due to
apps like RSX running in the background all the time.
Change-Id: I9f32d5f2e05b6697a8aaa9ddf74474b5531bb7e1
[ROCm/clr commit: 2f00782829]
Note that this requires base driver CL#2340320+ to have SQ interrupt
functionality enabled by default.
Change-Id: I04b936819ebe1eb7cf5de1db4fafe83af3a1b5f6
[ROCm/clr commit: 4171e9e0a3]
This module will be used to add any specific compiler options to ROCclr
and it's clients.
Currently it only adds a workaround to remove the MSVC flag /GR, which
is added by default CMake <3.20. This resolves the conflict of PAL
adding /GR-.
Change-Id: If83adb271bcec86812a6e9de940da3920fc75393
[ROCm/clr commit: ce9182e62b]
Below logic allocates the host buffer whenever a subbuffer is created
from a SVM allocation. This is only needed for multi-device contexts.
HIP does not support multi-device contexts, hence this logic just ends
up performing unnecessary system allocations.
Change-Id: I8eae635f7c5289c52ef73434218c1658b788a456
[ROCm/clr commit: ffbf368f4c]
This reverts commit 9df70fa03ce60d47247eb0e8f278e1f8dbd33d6e.
Reason for revert: need SWDEV-294782 to be resolved before we can enable SQ interrupt support.
Change-Id: I328170b60f1a3aab28c0b1fd3191297a1a51ecb7
[ROCm/clr commit: 6566361144]
Below logic is causing a crash in the CL-GL interop. As a workaround,
limit it only to HIP.
Change-Id: I12e81d035ebd80a4a9a09eb6eea2fae7040d90c9
[ROCm/clr commit: 74ccf71d53]
CMake always searches system paths for specified files before resorting
to the hints we give it. We should not be using elf and GL headers
from /usr/include.
Change-Id: I2172ce3da9cc101ced63e22d95ecc031b94f0a67
[ROCm/clr commit: a2612343d5]
Currently ADL is only being included if we build HSAIL and not LC. The
only configuration that does this is Ellesmere on Linux.
As the appprofile logic doesn't do anything right now, it should be
safe to remove it.
Change-Id: I13ce8c27af08c25b95edcbfd2ee1ce447b0bfd39
[ROCm/clr commit: 6ff4839d76]
Revert back to using the Raven (gfx902) target ID for Raven 2 (gfx909).
This is due to the HSAIL compiler not supporting gfx909.
In theory there should be no issue with running Raven isa on Raven 2.
Change-Id: I425edebc99075799eda5522fad231b8fb3184873
[ROCm/clr commit: 0b1481d4f1]
All KMD/asic_reg/UGL headers are located under the drivers folder. No
need for the AMD_UGL_PATH variable as it essentially is
${AMD_DRIVERS_PATH}/ugl.
Change-Id: I070d737d50f2096493b3e75ef9b9e824cb19d048
[ROCm/clr commit: 1423c1db64]
This change refactors the current ROCclr cmake build to accomodate a
more modular approach. This allows easier support for multiple compiler
and/or multiple runtime backends.
Currently supported compilers:
HSAIL - enabled by ROCCLR_ENABLE_HSAIL (defaults to OFF)
LC - enabled by ROCCLR_ENABLE_LC (defaults to ON)
Currently supported runtimes:
HSA - enabled by ROCCLR_ENABLE_HSA (defaults to ON)
PAL - enabled by ROCCLR_ENABLE_PAL (defaults to OFF)
Any configuration is supported as long as at least one compiler and one
runtime is enabled.
Since ROCclr clients can configure it differently, one cannot reuse the
same ROCclr build artifacts between different clients. To assure this,
this patch assumes that ROCclr will be built as part of the clients
project.
Change-Id: Id4a5c43634296802b8ae87d1ad5984968391ccaf
[ROCm/clr commit: 7f0c18457d]
HIP should be built with HSAIL support disabled.
Currently HSAILProgram::info() and VirtualGPU::buildKernelInfo() expose
ACL interfaces directly. This should not be allowed.
Change-Id: Iae15d4f19be16806826f2f6cb600752c11f97fc1
[ROCm/clr commit: bbe6246f19]
Currently LiquidFlash cannot be supported from Github Enterprise,
hence we need to be able to build with out it.
Allow this by setting -DWITH_LIQUID_FLASH=0.
Change-Id: I975e8ee16b7ba033e3eb95fe40955d8c1d4779b7
[ROCm/clr commit: 7034e749e3]
aclutGetTargetInfo() is an internal compiler lib helper functions. This
will not be imported in the HSAIL shared library build, however it is
simple enough that we can maintain our own local copy of it.
Change-Id: I91d1a336c7da027bf8a7df8fae86a25add533611
[ROCm/clr commit: 7fd1e9c10a]
Enabling both LC and HSAIL will cause the DYN macro to be redefined.
Rename it for each compiler to avoid name clashing.
Change-Id: I607f022f37c4d05bef4e3a8070d19bd3659d7bc2
[ROCm/clr commit: b771377665]
This change makes HSAIL usage similar to that of Comgr. By default, the
runtime will statically link against it, however if HSAIL_DYN_DLL is
defined, then the runtime will try to dynamically load HSAIL.
Currently stick to statically linking to HSAIL. In a feature patch the
dynamic loading behaviour will be enabled.
Change-Id: I6a78a4375975cf847f236b200404c8cf941d012b
[ROCm/clr commit: c7b50bb890]
In adition to removing the HSAIL logic from the ROCm backend, guard all
of the HSAIL includes in the common layer behind the WITH_COMPILER_LIB
define. This is to avoid including HSAIL headers when building with
no support for it.
In common logic replace the use of the aclType enum with the new
Program::file_type_t enum. This is essentially a local copy of the HSAIL
enum to avoid including any HSAIL headers.
Change-Id: Ica0651d1b29dfccc255cc584eb82a5cb35e1b520
[ROCm/clr commit: cbeb372e46]
Since the majority of the Hostcall implementation now sits in the
commmon layer, the PAL backend simply just needs to invoke it. One thing
that is missing though is HSA signal support.
The newly added pal::Signal class is a light emulaion of what HSA
signals provide. The current implementation is just enough to get
Hostcall working, but it can be expanded in the future if needed to
fully emulate HSA signals.
The major difference for now between PAL and ROCm hostcall
implemenations is that PAL doesn't support blocking signals. This will
be enabled in the near future. For now use active wait for PAL.
Change-Id: I746557354ab9d71a7d4a31f9320fcc2fee5aee7f
[ROCm/clr commit: 99e8ac55cd]
Since the allocation can be a suballocation, we should print both the
VA range for the allocation and the underlying memory object.
Change-Id: Ic9c707bbb78113b366d1b2c688e6fd33bdc8fd94
[ROCm/clr commit: 9e8a2f3266]
The settings need to be populated ASAP, otherwise the dummy context is
not created properly.
Change-Id: Iede0066308bb601dc68164e894775a646a0372f1
[ROCm/clr commit: 263173914f]
This change unifies the hostcall implementation for all the backends,
by pushing the common logic to the device layer. This is done by
replacing the use of hsa_signal_t with device::Signal (a light wrapper
around it).
Change-Id: I7b6fca7930b5a0b199da5d85e2e048354cc04e7b
[ROCm/clr commit: 671778bdd3]
PAL doesn't perform chunking for system memory allocations, hence we
should fall back to using pinned memory for mapping large buffers.
Change-Id: I1b472616b72d12ed0105fb65532acacdb98ac7b3
[ROCm/clr commit: b4e212a0f9]
PAL may internally align up the allocation size to the page size
reported by KMD. This will cause a mismatch in size between OCL and PAL.
To avoid this, use PAL size when updating the free memory counter on
both alloc and free.
Change-Id: Ic6e8c861a52170476474fb70a769eef93be3261f
[ROCm/clr commit: be66e29e94]
On ReBar systems the invible heap is not present, so in theory we should
fail creating the suballocation chunk, however PAL doesn't report any
errors.
To make sure we never fail, allow creating the allocation in the visible
heap and system memory.
Change-Id: Iea9cc68d98b9cb396a2b7a37398b98b66274083b
[ROCm/clr commit: 330b674821]
This is helpfull to do when debugging issues on lowend asics. Navi14 can be emulated as Navi10. So can Navi22 be emulated as Navi21.
Change-Id: I693ffd45a5b03657822afdc872781901bc69b65c
[ROCm/clr commit: 26d1b28b16]
With the PAL_ALWAYS_RESIDENT flag memory objects are resident at allocation time, no need to make them resident again before submit.
Also we should never evict anything with this setting, or we'll generate a VM fault.
Change-Id: Ieacc6af88ab4e09c20efd94100e148b2502e1d70
[ROCm/clr commit: fd09a7a23c]
The os.hpp header gets added to the include path of legacy llvm via the compiler lib. Having "windows.h" included causes a lot conflicts with LLVM headers, as they forward declare many Windows types. Best to not include it here.
Change-Id: I60c44a8d28660368f1a4a95741e1053ef3528fa1
[ROCm/clr commit: e1b916260a]
SWDEV-245906
All asics will still be supported for developer builds.
Change-Id: I0eac2246162d133fe63449c200d996fe05bd51bd
[ROCm/clr commit: 24c1c48db7]
This reverts commit bc5075c2c5.
This change broke the legacy-complib build in p4. It seems that we can't use any flags in debug.cpp.
Change-Id: I17bb83651b85d6f415d9074634b479658fd4c3f9
[ROCm/clr commit: 20c24cae93]
Enabling anything beyond -Wall like -Wextra or -pedantic seems impossible as our code base explodes in thousands of warnings.
-Wno-unused-{variable/function} is not present in the p4 build, but with gcc7.4.0 we get hundreds of instances of this warning being triggered in the code base.
With this change only two warnings show up during the build - -Wsequence-point and -Wunused-but-set-variable. The fix for the first is alredy in review.
Change-Id: I2ff37981377487b0e07fd9490498e38a60792c0c
[ROCm/clr commit: 947dbe82fb]
Bottom layers don't error check this value, so we might and up writing a bad value to a register and cause the SPI to hang.
Change-Id: I6da4ae71c66a25c63ebb804da4afe4ca7fb831b7
[ROCm/clr commit: 6e985845b3]
Don't error when querying the number of devices if there are no devices present in the system.
We should just return 0 for the number of devices in this case and let the application handle this situation.
Change-Id: I20614ade5e649f3ce9ddd970d4b38bfe296f6cdb
[ROCm/clr commit: 2a223ecec6]
Each WGP consists of 2 CU, so the number of available SIMD units is doubled.
Change-Id: I43978a8a9139c33f5f776b344a36bee927cc187d
[ROCm/clr commit: e76d867740]
cl_bool needed to be replaced with uint32_t instead of bool. This is due to cl_bool being a typedef of cl_uint32.
Currently clGetDeviceInfo() reports incorrect size for the return value, due to cl_bool being 4 bytes and c++ bool being 1 byte.
Change-Id: I647a4b8873627059865c84c8ca27694dbc0916de
[ROCm/clr commit: 243a3c2aa4]
When we're aligning rowPitch to imagePitchAlignment, rowPitch is in pixels,
but imagePitchAlignment_ is bytes, so we end up overaligning the pitch.
Convert imagePitchAlignment_ to pixels before doing any logic.
Change-Id: Ia5ab9d54bed150fe974e86b060dbadc196165b29
[ROCm/clr commit: 696d00e71b]
hip_threadfence_system passes locally with this change. This also fixes
hipHostMalloc() failures when hipHostMallocMapped flag is used.
Change-Id: Id412efe502accc7c6e7676b52c05ccb9d8fbbe67
[ROCm/clr commit: 5de65ba4a0]
Vladislav Sytchenko