Enable this optimization when the barrier is disabled, since
reuse requires a signal wait.
Use the size of pending AQL signals as the size of signal pool.
Change-Id: I2754a0f8b67e19d2601c58945e10fdf0e8be1624
[ROCm/clr commit: a5661192b6]
On ReBar systems the invible heap is not present, so in theory we should
fail creating the suballocation chunk, however PAL doesn't report any
errors.
To make sure we never fail, allow creating the allocation in the visible
heap and system memory.
Change-Id: Iea9cc68d98b9cb396a2b7a37398b98b66274083b
[ROCm/clr commit: 330b674821]
Now rocm/rocdevice.cpp also includes comgrctx.hpp, and we don't want to statically link against comgr when buidling shared libs.
Change-Id: Ic330bd860559b3e07b776c951afe6126b0f43f7d
[ROCm/clr commit: b38317cb3c]
This is helpfull to do when debugging issues on lowend asics. Navi14 can be emulated as Navi10. So can Navi22 be emulated as Navi21.
Change-Id: I693ffd45a5b03657822afdc872781901bc69b65c
[ROCm/clr commit: 26d1b28b16]
With the PAL_ALWAYS_RESIDENT flag memory objects are resident at allocation time, no need to make them resident again before submit.
Also we should never evict anything with this setting, or we'll generate a VM fault.
Change-Id: Ieacc6af88ab4e09c20efd94100e148b2502e1d70
[ROCm/clr commit: fd09a7a23c]
The change reuses HSA signals for dispatches as a wait signal.
Skipping the barrier requires to disable L2 cache for sysmem
allocations and extra tracking for HDP access with the large bar.
ROC_BARRIER_SYNC=0 activates the new logic. Barrier sync is
still used by default.
ROC_ACTIVE_WAIT=1 enables unconditional active wait in ROCr.
The change also consolidated ROCr wait logic under single function.
Change-Id: I6bd1be30aa88258da1b1f9de319ef5a45852afd8
[ROCm/clr commit: d9397590de]
SWDEV-249719 - root cause: queues with custom CU mask are not inserted
into queuePool_ (i.e., queue of reusable HSA queues) of ROC device class
causing a crash when creating hostcall buffers for printf
Change-Id: Ieee7005d9a5a30b3113394ce23ee65927126d0d6
[ROCm/clr commit: 2e199bd492]
The progvar_prog_scope_misc test expects CL_DEVICE_MAX_MEM_ALLOC_SIZE to be multiple of integer.
Change-Id: Ic0690f5ab06ffa3feafb718beabbcf83ab53978c
[ROCm/clr commit: 740f1ba0aa]
Replace amd::Atomic with std::atomic. Remove make_atomic uses by
converting the variable to std::atomic and making sure the memory
order is relaxed when synchronizes-with is not needed.
Delete utils/atomic.hpp.
Change-Id: I0b36db8d604a8510ac6e36b32885fd16a1b8ccfa
[ROCm/clr commit: 5d4b6f74d3]
1.Some files are not built in rocclr so the issues are
not found in rocclr build. But the issues are exposed
in TC build.
2.Clear unused codes in test cmake file.
Change-Id: I1ad4decdf4df5237b93e1ea2547eb39a19f7dc4a
[ROCm/clr commit: 65075e72f1]
Replace constexpr with const in kernel source
codes because some kernel compiler doesn't
support constexpr.
Replace scheduler with __amd_rocclr_scheduler
due to name change.
Change-Id: I1ad4ddcdf1df5237b83e1ea2447eb39a19f7dc4a
[ROCm/clr commit: 9c5465f9e1]
When header==0, the legitimate packet->header is wiped out, so also add an assert.
Change-Id: I6b3037d4618719262b0d7c1792bd54f768a63660
[ROCm/clr commit: 19d1497fa2]
root cause - cooperative queue is not inserted into queuePool_ (HSA queues) of ROC device calss causing a crash when creating hostcall buffers for printf
Change-Id: I3f9aceb4e5fe6a7c7a2a549a4bb0a3511fe02799
[ROCm/clr commit: d2b9d267b2]
German Andryeyev
Alex Xie
Rahul Garg
Vladislav Sytchenko
Jason Tang
agodavar
Sarbojit Sarkar
Tao Sang
Jatin Chaudhary
kjayapra-amd
Jason Tang
Aryan Salmanpour
Satyanvesh Dittakavi
Laurent Morichetti