Граф коммитов

2519 Коммитов

Автор SHA1 Сообщение Дата
Philip Yang b6e18ceeae kfdtest: Skip ContiguousVRAMAllocation if no enough VRAM
RDMATest.ContiguousVRAMAllocation test uses 4GB buffer, skip the test if
total VRAM size is less than 5GB, considering page table and other
reserved VRAM usage.

Change-Id: I0342417501cdd3477c2bf1b2f7d1e6bef61d1871
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 42df8b2b34]
2024-07-18 10:20:05 -05:00
Chris Freehill 405b60af73 Use static drm and drm_amdgpu for static builds
This commit was ported from old repo.
Original author: Ranjith Ramakrishnan <Ranjith.Ramakrishnan@amd.com>

For static builds use drm and drm_amdgpu static libraries for linking.

Created a separate cmake target file and static library for static use case

The config file will include the respective target file based on
BUILD_SHARED_LIBS.

Default target file will be the one where drm and libdrm_amdgpu shaed libraries
are linked.

Applications using statically linked cmake targets of hsakmt should install the
required static libraries before building.

Change-Id: Idf4e1a2b5f18b344f5a9927803756d50c2b33702


[ROCm/ROCR-Runtime commit: 9e8477e1c9]
2024-07-18 10:19:49 -05:00
Chris Freehill 3d3704582b Use staticdrm target of hsakmt for static build
This will link static libraries of drm and libdrm_amdgpu libraries

This commit was ported from old repo and originally authored by:
Ranjith Ramakrishnan <Ranjith.Ramakrishnan@amd.com>
Date: Thu, 20 Jun 2024 08:29:03 -0700

Change-Id: I8b06811516335317d4fb3d7c98b001a12776a808


[ROCm/ROCR-Runtime commit: 2a5e433393]
2024-07-17 22:45:50 -05:00
Tim Huang a85b7afd2e Fix last AMDGCN-based processors enumerator error
Change-Id: Idd0659a327585b30b0f7d4dcb9e2212b55239941
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 1278ac25c0]
2024-07-17 22:32:23 -05:00
David Belanger 19fc2d70ab Fix overflow in max_slice variable for GFX12
Change max_slice type to uint64_t and calculation to 64-bit, otherwise
value overflows to 0.

Problem triggered only on GFX12 as field size was increased.

Change-Id: If26451224538743dabc41bdc1b327c6ef021bc24
Signed-off-by: David Belanger <david.belanger@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 13c3f06dfe]
2024-07-17 22:32:23 -05:00
Lang Yu f2f5585a73 Fix Memory_Atomic_Add_Test issue
Since "libhsakmt: Prevent hsaKmtRegisterMemory* from registering non-userptr",
non-userptr is not allowed to be pinned any more.
Use hsa_amd_agents_allow_access to map host memory.

Change-Id: I898d2f83222907de58cafc1a2b18a636634d1b20
Signed-off-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 7e6c3d1bfa]
2024-07-17 22:32:23 -05:00
David Belanger 55761ca4a5 Fix image issue on GFX12
Fix encoding of pitch in SRD (1 bit missing).
Issue affects images with pitch > 8192.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: Id0b431f51ab3984d1a47d3e8c13d35e28a6009cf
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 4f453f3bd4]
2024-07-17 22:32:23 -05:00
Chris Freehill a80d7ad7cf Set PARENT_SCOPE for HSA_DEP_ROCPROFILER_REG
This variable is now in a sub-project, but needs to be visible
in the super-project.

Change-Id: I14d307646253df8f0a8a50d01b8ca677b904234c


[ROCm/ROCR-Runtime commit: 5820fa37d7]
2024-07-17 17:52:59 -05:00
Chris Freehill ee266668ab Add PROVIDES "hsa-rocr-dev,hsa-ext-rocr-dev" for RPMs
Change-Id: If2c4ef2dfdb89d4f2287b81e421815b27d0bcfb9


[ROCm/ROCR-Runtime commit: bdefad8028]
2024-07-09 22:51:32 -05:00
Chris Freehill 4bcdb4a2db Fix hsakmt-roct-devel REQUIRES/PROVIDES CPack handling
Change-Id: If8bac85f2f7a23bce1b967fcec25216603b4c7bd


[ROCm/ROCR-Runtime commit: 9830e32e7a]
2024-07-03 16:46:00 -05:00
David Yat Sin 140b5fbd40 Add hsa_amd_vmem_address_reserve_align API
New API to support alignment parameter when reserving virtual addresses.
If the alignment is 0, then the default size is used. Otherwise the
alignment needs to be a power of 2 and greater than or equal to page
size.

Existing hsa_amd_vmem_address_reserve marked for future deprecation.

Change-Id: I17cee75420183dea5842fc1ecc2514cdcd760bac
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 08c44fbda6]
2024-06-25 12:57:22 -05:00
AravindanC 2d6be55401 Static package generation for rocrtst
Change-Id: I465d542bc223db9c620fde72137012c61eff1ac3
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Signed-off-by: Aravindan Cheruvally <Aravindan.Cheruvally@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 81825df44d]
2024-06-25 12:50:03 -05:00
Yifan Zhang 491275f838 Add support for GC 11.5.2
Change-Id: Iad8604881dc66108933ac2155fef3b74bca9ac3f
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 71494a920b]
2024-06-25 12:50:03 -05:00
Ranjith Ramakrishnan 6f4013e1af Update elf library search path with lib64 path as well
The elf libraries are installed in /usr/lib64 in RHEL.
Removed invalid paths

Change-Id: I8c2b5525c1e3b62a2bd4e31a442d9931005c2f30
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 14ed20e0cc]
2024-06-25 12:50:03 -05:00
Vladimir Indic 7422cc3ae0 PC Sampling: Add s_nop prior to s_sendmeg
Add s_nop before s_sendmsg. This is required because the HW does not
check for dependencies for SALU writes to M0.

Section 4.5: Manually Inserted Wait States (NOPs)
"AMD Instinct MI200" Instruction Set Architecture
https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/instinct-mi200-cdna2-instruction-set-architecture.pdf

Change-Id: I90f503e3cc80cd29eab8bafa2565699461654055
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: c15e5d0e9d]
2024-06-25 12:50:03 -05:00
Chris Freehill c7538dba4e Add preinstall script for build_hsa.sh
This is to fix the situation where libhsa-runtime exists in
/usr/lib. The preinstall script will check for this and ask
the user if they want to delete the old version, or else
abandon install.

Change-Id: I0976b6ec95b9752c95031f1a73fc49a150b02b23
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 4474dcff2c]
2024-06-25 12:50:03 -05:00
Lancelot SIX b9cead955f trap_handler_gfx12: fix-math-excp-size
The current trap handler defined:

    .set SQ_WAVE_EXCP_FLAG_USER_MATH_EXCP_SHIFT    , 0
    .set SQ_WAVE_EXCP_FLAG_USER_MATH_EXCP_SIZE     , 6
    .set SQ_WAVE_TRAP_CTRL_MATH_EXCP_SHIFT         , 0
    .set SQ_WAVE_TRAP_CTRL_MATH_EXCP_SIZE          , 6

However, the ALU exception in EXCP_FLAG_USER go from bit 0 (alu_invalid)
to bit 6 (alu_int_div0), making it a total of 7 bits, not 6.  Similarly,
the corresponding bits in TRAP_CTRL go from bit 0 to 6 as well.

Fix the incorrect size to be sure to properly detect the int_div0
exception.

Change-Id: I60c2d94a447b71ca0ce26a87b7f55b055b9aef8e
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: cb8705627f]
2024-06-25 12:41:53 -05:00
Yifan Zhang 5510695ac8 GFX1150: remove dupilcated definition of GFX1150
This patch is to remove duplicated definition of GFX1150.

Change-Id: I4a8b8bce5c2721748c4d64e1da13b59feae2139a
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 1d1a32d725]
2024-06-25 12:41:53 -05:00
David Yat Sin 08626b6cf9 Move addrlib into rocr namespace
This avoids conflicts in case application is loading another copy of
addrlib.

Change-Id: Ifb4a10270c867366d5eed0a8c015257b415189a5
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: f1a13b6d87]
2024-06-25 12:41:53 -05:00
David Yat Sin 60e43e8dec VMM: return error if memory-only handle alloc fail
Return HSA_STATUS_ERROR_OUT_OF_RESOURCES if thunk call to allocate
memory handle returns NULL.

Change-Id: I6cf74f93f7d606416414ea7c2354db86aeef3137
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: beb9a42998]
2024-06-25 12:41:53 -05:00
Shweta Khatri 5f30d083d0 Revert "Added new ROCr Trap Handler Test"
This reverts commit b156e906d9c192bd487d10a8900e3eb6090ef547.

Reason for revert: Memory violation test causing a timeout in subsequent test.

Change-Id: If3a217575af545a47d6d67bebba4a2c640a43b81
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 2e1f363d2f]
2024-06-25 12:27:09 -05:00
Lancelot SIX 08a91d3db0 trap_handler_gfx12: Do not override STATE_PRIV.BARRIER_COMPLETE
The value of STATE_PRIV is captured by the 1st level trap handler, and
passed on to the second level trap handler.  The value is to be restored
before exit.  However it is possible for the value of
STATE_PRIV.BARRIER_COMPLETE to change while the wave is in the trap
handler (all the other waves in the workgroup has signaled the
work-gropu barrier), and in this case restoring STATE_PRIV in full would
result in STATE_PRIV.BARRIER_COMPLETE to be cleared.

Restore every bits of STATE_PRIV except for BARRIER_COMPLETE before
return to prevent this race.

Change-Id: I76c875bced7d23c58670b28f257d22c933f99fc5
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 9e625307d2]
2024-06-25 12:27:09 -05:00
Jonathan Kim 1918883414 Disable large copies for gfx94x
GFX94x runs into performance regression when doing large packet
enqueues.

Drop back to legacy packet sizes for now.

Change-Id: I595838ebada66c6c5143bfdb2f56c83ee71654a9
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: b8aae52404]
2024-06-25 12:27:09 -05:00
Shweta.Khatri e7af8fb99a Added new ROCr Trap Handler Test
Intentionally trigger sw exceptions to verify GPU can handle abnormal scenarios

Change-Id: Ie80aa21883a912834ce6d917ecbb21ff6b3145f5
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 6f6f02f352]
2024-06-25 12:27:09 -05:00
David Yat Sin 0f08f53c76 Remove debug bits set in forbiddenBlock
Removing extra bits set in forbiddenBlock that seemed to be set for
debugging and are causing unexpected image formats to be used.

Change-Id: I29c9e319907027a2b0b6bf7c1c0c8558eb6a36f4
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: e721eb509b]
2024-06-25 12:27:09 -05:00
David Yat Sin 49748c974b Update Addrlib gfx10 files
Update changes to  gfx10 addrlib files from:
https://gitlab.freedesktop.org/mesa/mesa.git

mesa top commit:
4d298673da9b05d826b960eece2e715a6b187330

Change-Id: I6015c827d3e9b1fbde034686432670958f424a1d
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: cf4b5e1598]
2024-06-25 12:27:09 -05:00
David Belanger 36fa572530 Implement SDMA_PKT_COPY_LINEAR_RECT for GFX12
Packet for GFX12 is incompatible with pre-GFX12 as some fields changed
location.   Implement code path and packet specific to GFX12.
This fixes some issues with SDMA blits and 3D images.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I56c204aaa12160e563ec960bd3b226cfa94e142d
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 6d147dd3b1]
2024-06-25 12:27:09 -05:00
David Belanger f5d734fcf4 Implement AddrLib support for GFX12
Add new files image_manager_gfx12.{h,cpp}.

Implement BUF/IMG/SAMP desc changes for GFX12.

Implement compute surface info code using AddrLib3 API (new starting
from GFX12).

Implement algorithm for choosing "best" swizzle mode (starting
from AddrLib3/GFX12, AddrLib provides only list of suitable swizzle mode,
up to client, ROCr, to choose the best).   Algorithm implemented follows
behaviour in GFX11 and behaviour for GFX12 on other platforms.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: Ib344c86228a98bbac5acdab421ee2ef9b1e84eef
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: f8a015f53e]
2024-06-25 12:27:09 -05:00
David Belanger 5565b53d15 Updated amd_aql_queue for GFX12
Added GFX12 implementation for InitScratchSRD and for compute_tmpring.
Implementation for compute_tmpring could be combined with GFX11 with some
refactoring as a possible future improvement.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I8013cbe4438786bf41bbfd03f6a5d3b9ef51e7bf
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: def4a6c326]
2024-06-25 12:27:09 -05:00
David Belanger bb7dcbc38b Added/Updated header files for AddrLib support (GFX12)
Updated struct definitions, field size changes and new fields in
registers.h.

Added resource_gfx12.h and updated fields in BUF/IMG/SAMP descriptor
structs based on documentation.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I08f05ba30f54c40e7b823a6a105829a1e8590b3d
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 8165da63cc]
2024-06-25 12:27:09 -05:00
David Yat Sin 8423772acb Disable extended-scope memory on gfx120x
Do not allow extended-scope fine-grain memory on gfx120x devices.

Change-Id: I1e6e6c1860de00160cca9d8137b129c7e32c0526
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 7dd90f8361]
2024-06-25 12:27:09 -05:00
David Belanger dd1079893a Updated makefile for GFX12 addrlib
Added GFX12 and AddrLib3 files, updated include paths.

Change-Id: I4880eadfd627b79ebcf2fe26b91649642911b050
Signed-off-by: David Belanger <david.belanger@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 288dea4c71]
2024-06-25 12:27:09 -05:00
David Belanger bb0a28b8c5 GFX12: Update addrlib
Updated address lib to mesa amd-temp-gfx12 branch.
Commit: 6e5244bd3184f0720197270a10e031b5ecd5fe75

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: Icaead4f38c5f3019c375116070b1f97a927f09b0
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: bb02f4e9a7]
2024-06-25 12:27:09 -05:00
Lancelot SIX 1b5596a7f2 trap_handler_gfx12.s: Fix access to EXCP_FLAG_PRIV
There is an issue in the gfx12 trap handler where the EXCP_FLAG_PRIV
is only fetched under certain conditions (trap_id != 0) while it should
have been fetched unconditionally.  As a consequence, the interrupt
payload might contain invalid data, leading to incorrect exceptions
being reported by the runtime.  Debugger is mostly un-affected as it
will inspect the wave's state to figure out what exception(s) have been
reported for each wave.

Also, it is not necessary to check for the host trap bit if trap_id is
!= 0 in gfx12, there is on trap ID anymore for host trap.

This patch implements those fixes.

Co-Authored-By: Laurent Morichetti <laurent.morichetti@amd.com>
Change-Id: Ib72cd8cc5d935ca643e241da7fccd3f96201b09d
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 7a3bf30769]
2024-06-25 12:27:09 -05:00
Lancelot SIX 211cb900ff trap_handler_gfx12.s: re-order constant declarations
The constant declarations in trap_handler_gfx12.s have been sorted
alphabetically, which causes inconsistencies.  Fix the order of
declarations where it makes sense.

Change-Id: I5b05d87a5afbe1ff3362746801a1c9373537b49e
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: ff9b11fd89]
2024-06-25 12:27:09 -05:00
Lancelot SIX 762bcc0391 Add GFX12 trap handler
Given the differences between previous architectures and gfx12, this
patch implements the gfx12 2nd level trap handler in a separate source
file, and adjusts the build system.

Change-Id: I65192ffbbcd66a4f78d2d0c3fb1739a92cac95d4
Signed-off-by: Lancelot SIX <lancelot.six@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 855015377c]
2024-06-25 12:27:09 -05:00
Sreekant Somasekharan 94950deac7 Initial GFX1201 changes.
Add target gfx1201 to several files.

Change-Id: I5cae7dba00ed58f8fbfa6e7147275bd7d5feaed0
Signed-off-by: Sreekant Somasekharan <sreekant.somasekharan@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 24463635f9]
2024-06-25 12:27:09 -05:00
David Belanger 78221f3e9b Add Blit shaders for GFX12
For GFX12, the workgroup id is passed in ttmp9 (trap temp register) instead of the scalar register.
Normal shader code (i.e. not priv, not trap handler) can only read the ttmp registers.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I42404d8c8c0ee9c746e23879fd30b2d16cfa1787
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 40cc6559f1]
2024-06-25 12:27:09 -05:00
Shweta.Khatri abc4fcabb5 Fix soft hang on AQLQueue destruction with a timeout
Add timeout to AQLQueue destructor signal wait to prevent indefinite hang

Change-Id: I6c6c98a7bdd27d39569af1d667aa9aa7e9596535
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 4e9647704d]
2024-06-25 12:27:09 -05:00
David Yat Sin 14f6875df2 Revert "Use pthread_setaffinity_np"
This reverts commit 1df7a44112e45b7fb447926778490f741601219a.

Change-Id: Ib386c8f944b6da0ef68ddd2be3f26013cd36ef5b
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 2f05c2a273]
2024-06-25 12:27:09 -05:00
David Yat Sin b4be8a2bfc Revert "Use pthread_attr_setaffinity_np when available"
This reverts commit ef95ccf81e59b8608861e8f2f256d981eee19df7.

Reason for revert: Causing performance regressions on some systems

Change-Id: I82951350cafbd57c495852d6f90023a3373f04f6
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 1cee8656df]
2024-06-25 12:27:09 -05:00
David Belanger adb5e2cabf Initial GFX12 changes.
Add target gfx1200 to several files.
Add cases for GFX12 in a few switch statements.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: Ib90032f5b9d5a3306060f13a43d970108a1399df
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 2f14acd9c1]
2024-06-25 12:27:09 -05:00
Ranjith Ramakrishnan 3b67f98663 Static package generation for hsa
Generate static package by combining binary and dev components.
Binary and dev component dependencies are added to the static package dependencies
No dependency to rocprofiler-register
Package name will have suffix static-dev/devel

Change-Id: I2f9680f13dbffc9eb7ced9fa9b28e360c47ebcca
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 696d8fae9e]
2024-06-25 12:27:09 -05:00
Tony Gutierrez 30d4499b2a driver: Add a core driver interface component
Add a new driver interface as a core ROCr component.

The driver component provides an interface for ROCr to interact with
agent kernel-model drivers in a generic way. This interface will be used
to interact with the XDNA NPU driver. Eventually, the ROCt library's
functionality should be implemented behind this interface.

For now the interface provides basic queue and memory allocation
for supporting HSA queues and signals and matches the thunk API
closely.

Change-Id: I37ac9f2dcbadc86ce45999f76b0e9ce753fd0c06
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 69ba32fa95]
2024-06-25 12:16:40 -05:00
Lang Yu fdad9350fb Simplify APU query
Query APU from thunk instead of parsing device id.

Change-Id: I95efa9e2a94fb979eaa88042991ee6921abbed7f
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 2f50b35daa]
2024-06-25 12:16:40 -05:00
Chris Freehill 76d33c555f Changes to build ROCr & thunk (optionally tests) in rocr-runtime repo
Create a new top-level CMakeLists.txt file to control building thunk
and ROCr. kfdtest and rocrtest are built separately.

Most of the cmake code that existed for thunk, ROCr, rocrtst and kfdtest
still reside in their respective CMakeLists.txt files, except the
CPack packaging directives which have been moved to the top-level
CMakeLists.txt.

Change-Id: I1a537359029504af8b1abb324bc6f0d75d98471e


[ROCm/ROCR-Runtime commit: 662f6817d7]
2024-06-24 14:26:21 -05:00
David Belanger 71da220fe7 Update AtomicIncIsa shader for GFX12
Minor instructions changes for GFX12.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: Iab2c430bb5d7d8fa2b166d07fd33ea15aca3a5cd
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 8917561625]
2024-06-24 14:26:21 -05:00
James Zhu 1ac98aa31a PC Sampling: Temporarily check KFD_IOCTL_MINOR_VERSION 16
Since PC Sampling is still under experiment, we can't
bump KFD_IOCTL_MINOR_VERSION to enable pc sampling.
KFD_IOCTL_MINOR_VERSION 16 already includes all pc sampling
code, so use version 16 to enable pc sampling implicitly for
customer to try-out this new feature.
Need update the version accordingly when pc sampling upstream.

Change-Id: I65840128f94e8f347c0617971c0aa4b7e478691a
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 338721c24a]
2024-06-24 14:26:21 -05:00
David Belanger 6457db7331 Update ScratchCopyDwordIsa shader for GFX12
Minor instructions changes for GFX12.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I57cca6393d4b4aae869a2bc9862d75eef1f29ed7
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: 9665499f83]
2024-06-24 14:26:21 -05:00
David Belanger 8238f92882 kfdtest: Update ReadMemoryIsa shader for GFX12
Minor instructions changes.

Change-Id: Iaa12763c6f7835aa658dbfb121e4963424b16745
Signed-off-by: David Belanger <david.belanger@amd.com>
Signed-off-by: Sreekant Somasekharan <sreekant.somasekharan@amd.com>
Signed-off-by: Chris Freehill <cfreehil@amd.com>


[ROCm/ROCR-Runtime commit: bc3f39a39e]
2024-06-24 14:26:21 -05:00